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Target Configuration Space
Table 7-4 · Capability Structure (Target-only cores with hot-swap and FIFO status)
31–24
23–16
15–8
7–0
Address
Upper Configuration Space
Reserved
Actel Capabilities
Hot-Swap
Size (12)
Next Pointer (00h)
Next Pointer (40h)
Capability ID (06h)
Capability ID (09h)
40h
44h
Interrupt Control Register
FIFO Status Register
Reserved
Reserved
Reserved
Reserved
Table 7-5 · Capability Structure (Master cores with hot-swap and FIFO status)
48h
4Ch
50h
54h
58h
5Ch
31–24
23–16
15–8
7–0
Address
Upper Configuration Space
Reserved
Hot-Swap
Next Pointer (00h)
Capability ID (06h)
40h
Reserved
44h
Actel Capabilities
Size (24)
Next Pointer (40h)
Capability ID (09h)
48h
FIFO Status Register
PCI Address
Backend Address/Data Value
Transfer Count
DMA Control Register
4Ch
50h
54h
58h
5Ch
Read-Only Configuration Registers
The following read-only registers, listed also in Table 7-1 on page 105 , have default values that are set by parameters.
See the PCI specification for further information on setting these values:
? Vendor ID
? Device ID
? Revision ID
? Class Code
? Subsystem ID
? Subsystem Vendor ID
? Maximum Latency and Minimum Grant
v4.0
107
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